HD64F2149YV datasheet(7/1075 Pages) RENESAS

7 / 1075 page

Rev. 3.00 Jan 18, 2006 page vii of xxviii

Main Revisions in This Edition

Item

Page

Revision (See Manual for Details)

All

—

All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors,

and other Hitachi brand names changed to Renesas

Technology Corp. Designation for categories changed from

“series” to “group”

4.5 Stack Status

after Exception

Handling

Figure 4.5(2) Stack

Status after Exception

Handling (Advanced

Mode)

Note

* deleted from figure 4.5(2)

104

Note *4 added to table 5.2

Name

Abbreviation

R/W

Initial Value

Address*

Wakeup event interrupt mask

WUEMRB

R/W

H'FF

H'FE44*

5.1.4 Register

Configuration

Table 5.2 Interrupt

Controller Registers

Note: 4. When setting WUEMRB, the MSTP0 bit in MSTPCRL

must be cleared to 0.

8.12.3 Pin Functions

Table 8.24 Port B

Pin Functions

264

Note

* added to table 8.24

Selection Method and Pin Functions

PB0/D0/

WUE0/

HIRQ3/

LSMI

The pin function is switched as shown below according to the combination of

the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and

bit PB0DDR.

Operating

mode

Mode 1,

modes 2 and 3 (EXPE = 1)

Modes 2, 3

(EXPE = 0)

LSMIE

—

HI12E

—

—*

CS3E

—

Either cleared

to 0

—*

ABW

——

—

PB0DDR

—

011

—*

Pin function

I/O pin

PB0

input

PB0

output

PB0

input

PB0

output

HIRQ3

output

LSMI

output

LSMI input pin

WUE0 input pin

Note:

When bit LSCIE is set to 1 in HICR0, bits HI12E and PB0DDR

should be cleared to 0.

Except when used as a data bus pin, this pin can always be used as the

WUE0 input pin.

The HIRQ3 output pin and

LSMI I/O pin can only be used in mode 2 or 3

(EXPE = 0).

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