HD64F2149YV datasheet(18/1075 Pages) RENESAS

18 / 1075 page

Rev. 3.00 Jan 18, 2006 page xviii of xxviii

10.3

Bus Master Interface ......................................................................................................... 301

10.4

Operation .......................................................................................................................... 304

Section 11 16-Bit Free-Running Timer......................................................................... 309

11.1

Overview........................................................................................................................... 309

11.1.1 Features................................................................................................................ 309

11.1.2 Block Diagram ..................................................................................................... 310

11.1.3 Input and Output Pins .......................................................................................... 311

11.1.4 Register Configuration......................................................................................... 312

11.2

Register Descriptions ........................................................................................................ 313

11.2.1 Free-Running Counter (FRC) .............................................................................. 313

11.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 313

11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 314

11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 315

11.2.5 Output Compare Register DM (OCRDM) ........................................................... 316

11.2.6 Timer Interrupt Enable Register (TIER) .............................................................. 316

11.2.7 Timer Control/Status Register (TCSR) ................................................................ 318

11.2.8 Timer Control Register (TCR) ............................................................................. 321

11.2.9 Timer Output Compare Control Register (TOCR) .............................................. 323

11.2.10 Module Stop Control Register (MSTPCR) .......................................................... 326

11.3

Operation .......................................................................................................................... 327

11.3.1 FRC Increment Timing ........................................................................................ 327

11.3.2 Output Compare Output Timing .......................................................................... 329

11.3.3 FRC Clear Timing................................................................................................ 330

11.3.4 Input Capture Input Timing ................................................................................. 330

11.3.5 Timing of Input Capture Flag (ICFA to ICFD) Setting ....................................... 333

11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)................................ 334

11.3.7 Setting of FRC Overflow Flag (OVF) ................................................................. 335

11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF ......................................... 335

11.3.9 ICRD and OCRDM Mask Signal Generation ...................................................... 336

11.4

Interrupts ........................................................................................................................... 337

11.5

Sample Application........................................................................................................... 338

11.6

Usage Notes ...................................................................................................................... 339

Section 12 8-Bit Timers..................................................................................................... 345

12.1

Overview........................................................................................................................... 345

12.1.1 Features................................................................................................................ 345

12.1.2 Block Diagram ..................................................................................................... 347

12.1.3 Pin Configuration................................................................................................. 348

12.1.4 Register Configuration......................................................................................... 349

12.2

Register Descriptions ........................................................................................................ 350

HD64F2149YV 数据表(PDF) 18 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 18 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载