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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HD64F2149YV 数据表(PDF) 30 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 30 Page - Renesas Technology Corp |
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30 / 1075 page  Section 1 Overview Rev. 3.00 Jan 18, 2006 page 2 of 1044 REJ09B0280-0300 Table 1.1 Overview Item Specifications CPU • General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control Maximum operating frequency: 10 MHz/3 V High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 100 ns (10-MHz operation) 16 × 16-bit register-register multiply: 2000 ns (10-MHz operation) 32 ÷ 16-bit register-register divide: 2000 ns (10-MHz operation) • Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions • Two CPU operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space Operating modes • Three MCU operating modes External Data Bus Mode CPU Operating Mode Description On-Chip ROM Initial Value Max. Value 1 Normal Expanded mode with on-chip ROM disabled Disabled 8 bits 16 bits 2 Advanced Expanded mode with on-chip ROM enabled Enabled 8 bits 16 bits Single-chip mode None 3 Normal Expanded mode with on-chip ROM enabled Enabled 8 bits 16 bits Single-chip mode None |
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