HD64F2149YV datasheet(21/1075 Pages) RENESAS

21 / 1075 page

Rev. 3.00 Jan 18, 2006 page xxi of xxviii

15.1.1 Features................................................................................................................ 425

15.1.2 Block Diagram ..................................................................................................... 427

15.1.3 Pin Configuration................................................................................................. 428

15.1.4 Register Configuration......................................................................................... 428

15.2

Register Descriptions ........................................................................................................ 430

15.2.1 Receive Shift Register (RSR) .............................................................................. 430

15.2.2 Receive Data Register (RDR) .............................................................................. 430

15.2.3 Transmit Shift Register (TSR) ............................................................................. 431

15.2.4 Transmit Data Register (TDR)............................................................................. 431

15.2.5 Serial Mode Register (SMR)................................................................................ 432

15.2.6 Serial Control Register (SCR).............................................................................. 435

15.2.7 Serial Status Register (SSR) ................................................................................ 438

15.2.8 Bit Rate Register (BRR) ...................................................................................... 443

15.2.9 Serial Interface Mode Register (SCMR).............................................................. 450

15.2.10 Module Stop Control Register (MSTPCR) .......................................................... 451

15.2.11 Keyboard Comparator Control Register (KBCOMP) .......................................... 452

15.3

Operation .......................................................................................................................... 454

15.3.1 Overview.............................................................................................................. 454

15.3.2 Operation in Asynchronous Mode ....................................................................... 456

15.3.3 Multiprocessor Communication Function............................................................ 467

15.3.4 Operation in Synchronous Mode ......................................................................... 475

15.3.5 IrDA Operation .................................................................................................... 484

15.4

SCI Interrupts.................................................................................................................... 487

15.5

Usage Notes ...................................................................................................................... 488

Section 16 I

2C Bus Interface............................................................................................. 493

16.1

Overview........................................................................................................................... 493

16.1.1 Features................................................................................................................ 493

16.1.2 Block Diagram ..................................................................................................... 494

16.1.3 Input/Output Pins ................................................................................................. 496

16.1.4 Register Configuration......................................................................................... 497

16.2

Register Descriptions ........................................................................................................ 498

16.2.1 I

2C Bus Data Register (ICDR) ............................................................................. 498

16.2.2 Slave Address Register (SAR) ............................................................................. 501

16.2.3 Second Slave Address Register (SARX) ............................................................. 502

16.2.4 I

2C Bus Mode Register (ICMR) ........................................................................... 503

16.2.5 I

2C Bus Control Register (ICCR) ......................................................................... 506

16.2.6 I

2C Bus Status Register (ICSR)............................................................................ 513

16.2.7 Serial/Timer Control Register (STCR) ................................................................ 519

16.2.8 DDC Switch Register (DDCSWR) ...................................................................... 520

16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 522

HD64F2149YV 数据表(PDF) 21 Page - Renesas Technology Corp

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