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HD64F2149YV 数据表(PDF) 406 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 406 Page - Renesas Technology Corp |
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406 / 1075 page  Section 12 8-Bit Timers Rev. 3.00 Jan 18, 2006 page 378 of 1044 REJ09B0280-0300 12.6.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.7. Table 12.7 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change Low 12.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 12.8, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. Erroneous incrementation can also happen when switching between internal and external clocks. |
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