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HD64F2149YV 数据表(PDF) 432 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 432 Page - Renesas Technology Corp |
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432 / 1075 page ![]() Section 13 Timer Connection Rev. 3.00 Jan 18, 2006 page 404 of 1044 REJ09B0280-0300 Table 13.8 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR Settings Register Bit(s) Abbreviation Contents Description 7CMIEB 0 6CMIEA 0 5OVIE 0 Interrupts due to compare-match and overflow are disabled 4 and 3 CCLR1, CCLR0 01 TCNT is cleared by compare-match A TCR in TMRY 2 to 0 CKS2 to CKS0 001 TCNT is incremented on internal clock: φ/4 TCSR in TMRY 3 to 0 OS3 to OS0 0110 0 output on compare-match B 1 output on compare-match A TOCRA in TMRY H'3F (example) IHG signal period = φ × 256 TOCRB in TMRY H'03 (example) IHG signal 1 interval = φ × 16 TCR in FRT 1 and 0 CKS1, CKS0 01 FRC is incremented on internal clock: φ/8 OCRAR in FRT H'7FEF (example) IVG signal 0 interval = φ × 262016 IVG signal period = φ × 262144 (1024 times IHG signal) OCRAF in FRT H'000F (example) IVG signal 1 interval = φ × 128 TOCR in FRT 6 OCRAMS 1 OCRA is set to the operating mode in which OCRAR and OCRAF are used |
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