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HD64F2149YV 数据表(PDF) 440 Page - Renesas Technology Corp

部件名 HD64F2149YV
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 440 Page - Renesas Technology Corp

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Section 14 Watchdog Timer (WDT)
Rev. 3.00 Jan 18, 2006 page 412 of 1044
REJ09B0280-0300
14.1.4
Register Configuration
The WDT has four registers, as summarized in table 14.2. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 14.2
WDT Registers
Address*
1
Channel
Name
Abbreviation
R/W
Initial Value
Write*
2
Read
0
Timer control/status
register 0
TCSR0
R/(W)*
3
H'00
H'FFA8
H'FFA8
Timer counter 0
TCNT0
R/W
H'00
H'FFA8
H'FFA9
1
Timer control/status
register 1
TCSR1
R/(W)*
3
H'00
H'FFEA
H'FFEA
Timer counter 1
TCNT1
R/W
H'00
H'FFEA
H'FFEB
Common
System control
register
SYSCR
R/W
H'09
H'FFC4
H'FFC4
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 14.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
14.2
Register Descriptions
14.2.1
Timer Counter (TCNT)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF flag in TCSR is set to 1. Watchdog timer overflow signal (
RESO) output,
an internal reset, NMI interrupt, interval timer interrupt (WOVI), etc., can be generated, depending
on the mode selected by the WT/
IT bit and RST/NMI bit.



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