HD64F2149YV datasheet(578/1075 Pages) RENESAS

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HD64F2149YV 数据表(PDF) 578 Page - Renesas Technology Corp

部件名	HD64F2149YV

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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578 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 550 of 1044

REJ09B0280-0300

• Notes on I2C Bus Interface Stop Condition Instruction Issuance

If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance

is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising

of the 9th SCL clock, issue the stop condition after reading SCL and determining it to below,

as shown below.

Stop condition

SCL

IRIC

[1] Determination of SCL = Low

9th clock

VIH

High period secured

[2] Stop condition instruction isuuance

SDA

As waveform rise is late,

SCL is detected as low

generation

Figure 16.20 Timing of Stop Condition Issuance

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