HD64F2149YV datasheet(585/1075 Pages) RENESAS

585 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 557 of 1044

REJ09B0280-0300

• Notes on TRS Bit Setting and ICDR Register Access

Conditions to cause this failure

Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are

satisfied.

 Master mode

Figure 16.26 shows the notes on ICDR reading (TRS = 1) in master mode.

(1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full).

(2) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)

(3) Sets to receive mode (TRS = 0), after transmitting Rev.1 frame of issued start condition

by master mode.

 Slave mode

Figure 16.27 shows the notes on ICDR writing (TRS = 0) in slave mode.

(1) Writes ICDR register in receive mode (TRS = 0), after entering the start condition by

slave mode (TDRE = 0 state).

Address match with Rev.1 frame, receive 1 by R/W bit, and switches to transmit mode

(TRS = 1).

When these conditions are satisfied, the low fixation of the SCL pins is cancelled

without ICDR register access after Rev.1 frame is transferred.

• Restriction

Please carry out the following countermeasures when transmitting/receiving via the IIC bus

interface module.

(1) Please read the ICDR registers in receive mode, and write them in transmit mode.

(2) In receiving operation with master mode, please issue the start condition after clearing the

internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the DDCSWR

HD64F2149YV 数据表(PDF) 585 Page - Renesas Technology Corp