HD64F2149YV datasheet(636/1075 Pages) RENESAS

部件名	HD64F2149YV

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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636 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 608 of 1044

REJ09B0280-0300

R/W

Name

Abbrevia-

tion

Slave

Host

Initial

Value

Slave

Address*

Host

Address*

Two-way registers 1 to 15

TWR1 to

TWR15

R/W

—

H'FE21 to

H'FE2F

LADR3*

+17/–15

LADR3*

+31/–1

SERIRQ control register 0

SIRQCR0

R/W

—

H'00

H'FE36

—

SERIRQ control register 1

SIRQCR1

R/W

—

H'00

H'FE37

—

Module stop control register

MSTPCRH

R/W

—

H'3F

H'FF86

—

MSTPCRL

R/W

—

H'FF

H'FF87

—

Notes: 1. Bits 5 and 3 are read-only bits.

2. The user-defined bits (channels 1 and 2: bits 7 to 4 and 2; channel 3: bit 2) are

read/write accessible from the slave processor.

3. Address when accessed from the slave processor. The lower 16 bits of the address are

shown.

4. Address when accessed from the host processor.

5. +0 and +4 address calculation is performed, with bit 0 of LADR3 regarded as B'0.

6. +31 to –16 address calculation is performed, with bits 3 to 0 of LADR3 regarded as

B'0000.

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