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HD64F2149YV 数据表(PDF) 690 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 690 Page - Renesas Technology Corp |
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690 / 1075 page ![]() Section 20 A/D Converter Rev. 3.00 Jan 18, 2006 page 662 of 1044 REJ09B0280-0300 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the A/D converter. Module data bus Control circuit Internal data bus 10-bit D/A Comparator + – Sample-and- hold circuit φ/8 φ/16 ADI interrupt signal AVCC AVref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6/CIN0 to CIN7 AN7/CIN8 to CIN15 ADTRG Conversion start trigger from 8-bit timer Legend: ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 20.1 Block Diagram of A/D Converter |
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