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HD64F2149YV 数据表(PDF) 787 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 787 Page - Renesas Technology Corp |
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787 / 1075 page ![]() Section 24 Power-Down State Rev. 3.00 Jan 18, 2006 page 759 of 1044 REJ09B0280-0300 24.5 Module Stop Mode 24.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 24.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter, 8-bit PWM module, and 14-bit PWM module, are retained. After reset release, all modules other than the DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. |
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