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HD64F2149YV 数据表(PDF) 874 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 874 Page - Renesas Technology Corp |
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874 / 1075 page ![]() Appendix A Instruction Set Rev. 3.00 Jan 18, 2006 page 846 of 1044 REJ09B0280-0300 Table A.4 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module 8-Bit Bus 16-Bit Bus Cycle On-Chip Memory 8-Bit Bus 16-Bit Bus 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch S I 1 4 2 4 6 + 2m 2 3 + m Branch address fetch S J Stack operation S K Byte data access S L 22 3 + m Word data access S M 4 4 6 + 2m Internal operation S N 11 1 1 1 1 1 Legend: m: Number of wait states inserted into external device access |
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