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HD64F2149YV 数据表(PDF) 151 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 151 Page - Renesas Technology Corp |
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151 / 1075 page  Section 5 Interrupt Controller Rev. 3.00 Jan 18, 2006 page 123 of 1044 REJ09B0280-0300 Address bus Break request signal Breakpoint NOP instruction is executed at breakpoint address H'0312 and next address, H'0314; fetch from address H'0316 starts after end of exception handling. φ Instruction fetch Internal operation Internal operation Vector fetch Stack save Instruction fetch H'0310 NOP execution H'0310 NOP H'0312 NOP H'0314 NOP H'0316 NOP NOP execution NOP execution Interrupt exception handling H'0312 H'0314 H'0316 H'0318 H'0036 SP-2 SP-4 • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction fetch Address bus Break request signal Breakpoint MOV instruction is executed at breakpoint address H'0312, NOP instruction at next address, H'0316, is not executed; fetch from address H'0316 starts after end of exception handling. φ Internal operation Internal operation Vector fetch Stack save Instruction fetch H'0310 NOP execution H'0310 NOP H'0312 MOV.W #xx:16,Rd H'0316 NOP H'0318 NOP MOV.W execution Interrupt exception handling H'0312 H'0314 H'0316 H'0318 H'0036 SP-2 SP-4 • Program area in on-chip memory, 2-state execution instruction at specified break address Address bus Break request signal Breakpoint NOP instruction at breakpoint address H'0312 is not executed; fetch from address H'0312 starts after end of exception handling. φ Instruction fetch Internal operation Internal operation Vector fetch Stack save H'0310 NOP execution H'0310 NOP H'0312 NOP H'0314 NOP H'0316 NOP Interrupt exception handling H'0312 H'0314 H'0036 SP-2 SP-4 • Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address Instruction fetch Instruction fetch Instruction fetch Instruction fetch Instruction fetch Instruction fetch Instruction fetch Instruction fetch Instruction fetch Instruction fetch Figure 5.6 Examples of Address Break Timing |
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