HD64F2149YV datasheet(220/1075 Pages) RENESAS

220 / 1075 page

Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 192 of 1044

REJ09B0280-0300

Table 7.9

Number of States Required for Each Execution Phase

Object of Access

On-

Chip

RAM

On-

Chip

ROM

Internal I/O

Registers

External Devices

Bus width

Access states

Vector read

—

——

46+2m

3+m

Execution

phase

information

read/write

—

———

—

Byte data read

222

3+m

Word data read

424

6+2m

3+m

Byte data write

222

3+m

Word data write

424

6+2m

3+m

Internal operation S

111

The number of execution states is calculated from the formula below. Note that

Σ means the sum

of all transfers activated by one activation event (the number for which the CHNE bit is set to one,

plus 1).

Number of execution states = I · S

I + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is transferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

HD64F2149YV 数据表(PDF) 220 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 220 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载