H8SSLASH2225 datasheet(210/1071 Pages) RENESAS

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Section 4 Exception Handling

Rev. 5.00 Aug 08, 2006 page 124 of 982

REJ09B0054-0500

Table 4.4

Status of CCR and EXR after Trace Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0

Trace exception handling cannot be used.

—

Legend:

Set to 1

Cleared to 0

—:

Retains value prior to execution

4.5

Interrupts

Interrupts are controlled by the interrupt controller. The interrupt control has two interrupt control

modes and can assign interrupts other than NMI to eight priority/mask levels to enable

multiplexed interrupt control. For details, refer to section 5, Interrupt Controller.

Interrupt exception handling is conducted as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended control

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution begins from that address.

4.6

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state.

Trap instruction exception handling is conducted as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended control

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

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