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H8S/2225 数据表(PDF) 211 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 211 Page - Renesas Technology Corp |
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211 / 1071 page ![]() Section 4 Exception Handling Rev. 5.00 Aug 08, 2006 page 125 of 982 REJ09B0054-0500 Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 01 — — — 21 — — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution 4.7 Stack Status after Exception Handling Figures 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. CCR CCR PC (24 bits) SP Note: * Ignored on return EXR PC (24 bits) SP (a) Interrupt control mode 0 (b) Interrupt control mode 2 Reserved* Figure 4.2 Stack Status after Exception Handling (Advanced Mode) |
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