H8SSLASH2225 datasheet(209/1071 Pages) RENESAS

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Section 4 Exception Handling

Rev. 5.00 Aug 08, 2006 page 123 of 982

REJ09B0054-0500

4.3.3

Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.L #xx,SP).

4.3.4

State of On-Chip Peripheral Modules after Reset Release

After reset release, MSTPCRA is initialized to H'3F, MSTPCRB and MSTPCRC are initialized to

H'FF, and all modules except the DMAC* and DTC enter module stop mode. Consequently, on-

chip peripheral module registers cannot be read or written to. Register reading and writing is

enabled when the module stop mode is exited.

Note: * Supported only by the H8S/2239 Group.

4.4

Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,

Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.4 shows

the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by

clearing the T bit in EXR to 0. Interrupts are accepted even within the trace exception handling

routine.

The T bit saved on the stack retains its value of 1, and when control is returned from the trace

exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling

is not carried out after execution of the RTE instruction.

H8S/2225 数据表(PDF) 209 Page - Renesas Technology Corp