ADE5166 datasheet(130/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 130 of 156

UART OPERATION MODES

Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12)

Mode 0 is selected when the SM0 and SM1 bits in the serial

communications control SFR (SCON, Address 0x98[7:6]) are

cleared. In this shift register mode, serial data enters and exits

through the RxD pin. The TxD pin outputs the shift clock. The

baud rate is fixed at fCORE/12. Eight data bits are transmitted or

received.

Transmission is initiated by any instruction that writes to the

serial port buffer SFR (SBUF, Address 0x99). The data is shifted

out of the Pin RxD line. The eight bits are transmitted with the

least significant bit (LSB) first.

Reception is initiated when the serial port receive enable bit,

REN (SCON[4]), is 1, and the serial port receive interrupt bit, RI

(SCON[0]), is 0. When RI is cleared, the data is clocked into the

Pin RxD line, and the clock pulses are output from the Pin TxD

line as shown in Figure 104.

RxD

(DATA OUT)

TxD

(SHIFT CLOCK)

DATA BIT 0

DATA BIT 1

DATA BIT 6

DATA BIT 7

Figure 104. 8-Bit Shift Register Mode

Mode 1 (8-Bit UART with Variable Baud Rate)

Mode 1 is selected by clearing the SM0 bit (SCON[7]) and setting

the SM1 bit (SCON[6]). Each data byte (LSB first) is preceded by

a start bit (0) and followed by a stop bit (1). Therefore, each frame

consists of 10 bits transmitted on the TxD pin or received on the

RxD pin.

The baud rate is set by a timer overflow rate. Timer 1 or Timer 2

can be used to generate baud rates, or both timers can be used

simultaneously where one generates the transmit rate and the

other generates the receive rate. There is also a dedicated timer

for baud rate generation, the UART timer, which has a fractional

divisor to precisely generate any baud rate (see the UART Timer

Generated Baud Rates section).

Transmission is initiated by a write to the serial port buffer SFR

(SBUF, Address 0x99). Next, a stop bit (1) is loaded into the ninth

bit position of the internal serial port shift register. The data is

output bit by bit until the stop bit appears on the TxD pin and

the transmit interrupt flag, TI (Address 0x98[1]), is automati-

cally set, as shown in Figure 105.

TxD

(SCON[1])

START

BIT

STOP BIT

SET INTERRUPT

(FOR EXAMPLE,

READY FOR MORE DATA)

Figure 105. 8-Bit Variable Baud Rate

Reception is initiated when a 1-to-0 transition is detected on

the RxD pin. Assuming that a valid start bit is detected, char-

acter reception continues. The eight data bits are clocked into

the internal serial port shift register.

All of the following conditions must be met at the time the final

shift pulse is generated to receive a character:

•

If the extended UART is disabled (EXTEN = 0 in the CFG

SFR, Address 0xAF[6]), RI (SCON[0]) must be 0 to receive

a character. This ensures that the data in the SBUF SFR is not

overwritten if the last received character has not been read.

•

If frame error checking is enabled by setting SM2 (SCON[5]),

the received stop bit must be set to receive a character. This

ensures that every character received comes from a valid

frame, with both a start bit and a stop bit.

If any of these conditions is not met, the received frame is irre-

trievably lost, and the receive interrupt flag (RI, SCON[0]) is

not set.

If the received frame meets these conditions, the following

events occur:

•

The eight bits in the receive shift register are latched into

the SBUF SFR.

•

The ninth bit (stop bit) is clocked into RB8 (SCON[2]).

•

The receiver interrupt flag (RI, SCON[0]) is set.

Mode 2 (9-Bit UART with Baud Rate Fixed at fCORE/64 or

fCORE/32)

Mode 2 is selected by setting SM0 and clearing SM1. In this mode,

the UART operates in 9-bit mode with a fixed baud rate. The

baud rate is fixed at fCORE/64 by default, although setting the SMOD

bit in the program control SFR (PCON, Address 0x87[7]) doubles

the frequency to fCORE/32. Eleven bits are transmitted or received:

a start bit (0), eight data bits, a programmable ninth bit, and a stop

bit (1). The ninth bit is most often used as a parity bit or as part

of a multiprocessor communication protocol, although it can be

used for anything, including a ninth data bit, if required.

To use the ninth data bit as part of a communication protocol for

a multiprocessor network such as RS-485, the ninth bit is set to

indicate that the frame contains the address of the device with

which the master wants to communicate. The devices on the net-

work are always listening for a packet with the ninth bit set and

are configured such that if the ninth bit is cleared, the frame is not

valid, and a receive interrupt is not generated. If the ninth bit is set,

all devices on the network receive the address and obtain a receive

character interrupt. The devices examine the address and, if it

matches one of the preprogrammed addresses of the device, that

device configures itself to listen to all incoming frames, even those

with the ninth bit cleared. Because the master has initiated commu-

nication with that device, all the following packets with the ninth

bit cleared are intended specifically for that addressed device until

another packet with the ninth bit set is received. If the address

does not match, the device continues to listen for address packets.

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