ADE5166 datasheet(134/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 134 of 156

UART2 SERIAL INTERFACE

The ADE5166/ADE5169/ADE5566/ADE5569 UART2 is an 8-bit

or 9-bit UART with variable baud rate.

Variable baud rates are defined by using an internal timer to

generate any rate between 300 bauds/sec and 115,200 bauds/sec.

The UART2 serial interface provided in the ADE5166/ADE5169/

ADE5566/ADE5569 is a full-duplex serial interface. It is also

receive buffered by storing the first received byte in a receive

buffer until the reception of the second byte is complete. The

physical interface to the UART is provided via the RxD2

(P0.7/SS/T1/RxD2) pin and the TxD2 (SDEN/P2.3/TxD2) pin,

whereas the firmware interface is through the SFRs presented in

Table 145

Both the serial port receive and transmit registers are accessed

through the SBUF2 SFR (Address 0xEB). Writing to SBUF2

loads the transmit register, and reading SBUF2 accesses a

physically separate receive register.

An enhanced UART2 mode is offered by using the UART2 timer

and providing enhanced frame error, break error, and overwrite

error detection. The SBAUD2 SFR (Address 0xEE) is used to

configure the UART2 timer and to indicate the enhanced

UART2 errors.

UART2 SFRs

Table 145. Serial Port 2 SFRs

SFR

Address

Bit

Addressable

Description

SCON2

0xE1

Serial Communications Control 2 (see Table 146).

SBUF2

0xEB

Serial Port 2 buffer (see Table 147).

SBAUD2

0xEE

Enhanced Serial Baud Rate Control 2 (see Table 148).

Table 146. Serial Communications Control 2 SFR (SCON2, Address 0xE1)

Bit

Mnemonic

Default

Description

N/A

Reserved.

EN-T8

9-bit UART, variable baud rate enable bit. When set, the UART2 is in 9-bit mode.

OWE2

Overwrite error. This bit is set when new data is received and RI2 = 1 in the SCON SFR. It indicates

that SBUF2 was not read before the next character was transferred in, causing the prior SBUF2

data to be lost. Write a 0 to this bit to clear it.

FE2

Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read

only and is updated every time a frame is received.

BE2

Break error. This bit is set whenever the receive data line (RxD2) is low for longer than a full

transmission frame, the time required for a start bit, eight data bits, a parity bit, and half a stop

bit. This bit is updated every time a frame is received.

REN2

Serial Port 2 receive enable bit. Set by user software to enable serial port reception. Cleared by

user software to disable serial port reception.

TI2

Serial Port 2 transmit interrupt flag. Set by hardware at the end of the eighth bit, TI2 must be

cleared by user software.

RI2

Serial Port 2 receive interrupt flag. Set by hardware at the end of the eighth bit, RI2 must be

cleared by user software.

Table 147. Serial Port 2 Buffer SFR (SBUF2, Address 0xEB)

Bit

Mnemonic

Default

Description

[7:0]

SBUF2

Serial Port 2 data buffer.

Table 148. Enhanced Serial Baud Rate Control 2 SFR (SBAUD2, Address 0xEE)

Bit

Mnemonic

Default

Description

TB8_2

Serial port transmit (Bit 9). The data loaded into TB8_2 is the ninth data bit transmitted in 9-bit mode.

RB8_2

Serial port receive (Bit 9). The ninth data bit received in 9-bit mode is latched into RB8_2. For

8-bit mode, the stop bit is latched into RB8_2.

SBF2

Fractional divider Boolean. When set, SBAUDF2 = 0x2B. When cleared, SBAUDF2 = 0x07.

[4:3]

SBTH2

Extended divider ratio for baud rate setting (see Table 149).

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