ADE5166 datasheet(133/156 Pages) AD

133 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 133 of 156

SBAUDF is the fractional divider ratio required to achieve the

required baud rate. The appropriate value for SBAUDF can be

calculated with the following formula:

SBAUDF = 64 ×

⎟

⎠

⎞

⎜

⎝

⎛

−

Rate

Baud

SBTH

DIV

CORE

Note that SBAUDF should be rounded to the nearest integer.

After the values for DIV and SBAUDF are calculated, the actual

baud rate can be calculated with the following formula:

Acutal Baud Rate =

⎟

⎠

⎞

⎜

⎝

⎛ +

SBAUDF

SBTH

DIV

CORE

For example, to obtain a baud rate of 9600 bps while operating

at a core clock frequency of 4.096 MHz and with the PLL CD

bits equal to 0

DIV + SBTH =

()

log

9600

4,096,000

log

⎟

⎠

⎞

⎜

⎝

⎛

= 4.74 = 4

Note that the DIV result is rounded down.

SBAUDF = 64 ×

⎟

⎠

⎞

⎜

⎝

⎛

−

9600

000

096

= 42.67 = 0x2B

Thus, the actual baud rate is 9570 bps, resulting in a 0.31% error.

UART ADDITIONAL FEATURES

Enhanced Error Checking

The extended UART provides frame error, break error, and over-

write error detection. Framing errors occur when a stop bit is

not present at the end of the frame. A missing stop bit implies

that the data in the frame may not have been received properly.

Break error detection indicates whether the RxD line has been low

for longer than a 9-bit frame. It indicates that the data just received,

a 0 or null character, is not valid because the master has discon-

nected. Overwrite error detection indicates when the received data

has not been read fast enough and, as a result, a byte of data has

been lost.

The 8052 standard UART offers frame error checking for an 8-bit

UART through SM2 (Bit 5) and RB8 (Bit 2) in the serial commu-

nications control SFR (SCON, Address 0x98). Setting the SM2 bit

prevents frames without a stop bit from being received. The stop

bit is latched into the RB8 bit. This bit can be examined to

determine if a valid frame was received. The 8052 does not,

however, provide frame error checking for a 9-bit UART. This

enhanced error checking functionality is available through the

frame error bit, FE, in the enhanced serial baud rate control SFR

(SBAUDT, Address 0x9E[6]). The FE bit is set on framing errors

for both 8-bit and 9-bit UARTs.

EXTEN = 1

STOP

START

Figure 108. UART Timing in Mode 1

STOP

START

EXTEN = 1

Figure 109. UART Timing in Mode 2 and Mode 3

The 8052 standard UART does not provide break error detection.

However, for an 8-bit UART, a break error can be detected when

the received character is 0, a null character, and when there is a

no stop bit because the RB8 bit is low. Break error detection is

not possible for a 9-bit 8052 UART because the stop bit is not

recorded. The ADE5166/ADE5169/ADE5566/ADE5569

enhanced break error detection is available through the BE bit

(SBAUDT[5]).

The 8052 standard UART prevents overwrite errors by not allowing

a character to be received when RI, the receive interrupt flag

(SCON[0]), is set. However, it does not indicate if a character

has been lost because the RI bit is set when the frame is received.

The enhanced UART overwrite error detection provides this infor-

mation. When the enhanced 8052 UART is enabled, a frame is

received regardless of the state of the RI flag. If RI = 1 when a

new byte is received, the byte in SCON is overwritten, and the

overwrite error flag, OWE2 in the Serial Communications

Control 2 SFR (SCON2, Address 0xE1[5]), is set. The overwrite

error flag is cleared when SBUF is read.

The extended UART is enabled by setting the EXTEN bit in the

configuration SFR (CFG, Address 0xAF[6]).

UART TxD Signal Modulation

There is an internal 38 kHz signal that can be OR’ed with the

UART transmit signal for use in remote control applications

(see the 38 kHz Modulation section).

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