ADE5166 datasheet(143/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 143 of 156

SPI INTERRUPT AND STATUS FLAGS

The SPI interface has several status flags that indicate the status

of the double-buffered receive and transmit registers. Figure 112

shows when the status and interrupt flags are raised. The transmit

interrupt occurs when the transmit shift register is loaded with the

data in the SPI/I2C transmit buffer SFR (SPI2CTx, Address 0x9A).

If the SPI master is in transmit operating mode and the SPI2CTx

SFR has not been written with new data by the beginning of the

next byte transfer, the transmit operation stops.

When a new byte of data is received in the SPI/I2C receive buffer

SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt flag,

SPIRxIRQ (SPISTAT, Address 0xEA[4]), is raised. If the data in

the SPI/I2C receive buffer SFR (SPI2CRx, Address 0x9B) is not

read before new data is ready to be loaded into the SPI2CRx

SFR, an overflow condition occurs. This overflow condition,

indicated by the SPIRxOF flag (SPISTAT[5]), forces the new data

to be discarded or overwritten, depending on the setting of the

RxOFW bit (SPIMOD1, Address 0xE8[2]).

SPITx

TRANSMIT SHIFT REGISTER

SPITxIRQ = 1

SPITx (EMPTY)

TRANSMIT SHIFT REGISTER

STOPS TRANSFER IF TIMODE = 1

SPIRx

RECEIVE SHIFT REGISTER

SPIRxIRQ = 1

SPIRx (FULL)

RECEIVE SHIFT REGISTER

SPIRxOF = 1

Figure 112. SPI Receive and Transmit Interrupt and Status Flags

SCLK

(SPICPOL = 0)

MISO

SCLK

(SPICPOL = 1)

MOSI

SPIRx AND

SPITx FLAGS

WITH INTMOD = 1

SPIRx AND

SPITx FLAGS

WITH INTMOD = 0

SPIRx AND

SPITx FLAGS

WITH INTMOD = 0

SPICPHA = 1

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MISO

MOSI

SPIRx AND

SPITx FLAGS

WITH INTMOD = 1

SPICPHA = 0

Figure 113. SPI Timing Configurations

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