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ADE5166/ADE5169/ADE5566/ADE5569

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Table 159. I2C Interrupt Status SFR (SPI2CSTAT, Address 0xEA)

Bit

Mnemonic

Default

Description

I2CBUSY

This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied.

I2CNOACK

I2C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device

does not send an acknowledgement. The I2C communication is stopped after this event.

Write a 0 to this bit to clear it.

I2CRxIRQ

I2C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.

Write a 0 to this bit to clear it.

I2CTxIRQ

I2C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.

Write a 0 to this bit to clear it.

[3:2]

I2CFIFOSTAT

Status bits for 3- or 4-byte deep I2C FIFO. The FIFO monitored in these two bits is the one currently

used in I2C communication (receive or transmit) because only one FIFO is active at a time.

I2CFIFOSTAT

Result

FIFO empty

Reserved

FIFO half full

FIFO full

I2CACC_ERR

Set when trying to write and read at the same time. Write a 0 to this bit to clear it.

I2CTxWR_ERR

Set when a write is attempted when the I2C transmit FIFO is full. Write a 0 to this bit to clear it.

READ AND WRITE OPERATIONS

SCLK

SDATA

START BY

MASTER

ACK BY

SLAVE

ACK BY

MASTER

FRAME 2

DATA BYTE 1 FROM MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

FRAME N + 1

DATA BYTE N FROM SLAVE

STOP BY

MASTER

NACK BY

MASTER

Figure 114. I2C Read Operation

SCLK

SDATA

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

FRAME 2

DATA BYTE 1 FROM MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

STOP BY

MASTER

R/W

Figure 115. I2C Write Operation

Figure 114 and Figure 115 depict I2C read and write operations,

respectively. Note that the LSB of the I2CADR SFR (Address 0xE9)

is used to select whether a read or write operation is performed

on the slave device. During the read operation, the master acknowl-

edgements are generated automatically by the I2C peripheral. The

master-generated no acknowledge (NACK) before the end of

a read operation is also automatically generated after the I2CRCT

bits in the I2CMOD SFR (Address 0xE8[4:0]) have been read from

the slave. If the I2CADR register is updated during a transmission,

the master generates a start condition instead of a stop at the end

of the read or write operation and then continues with the next

communication.

Reading the SPI/I2C Receive Buffer SFR (SPI2CRx,

Address 0x9B)

Reading the SPI2CRx SFR should be done with a 2-cycle

instruction, such as

Mov a, spi2crx or Mov R0, spi2crx

A 3-cycle instruction, such as

Mov 3dh, spi2crx

does not transfer the right data into RAM Address 0x3D.

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