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ADE5166/ADE5169/ADE5566/ADE5569

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Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)

Bit

Mnemonic

Default

Description

BUSY

SPI peripheral busy flag.

BUSY

Result

The SPI peripheral is idle.

The SPI peripheral is busy transferring data in slave or master mode.

MMERR

SPI multimaster error flag.

MMERR

Result

A multiple master error has not occurred.

If the SS_EN bit (SPIMOD1, Address 0xE8[3]) is set, enabling the slave select input and asserting

the SS pin while the SPI peripheral is transferring data as a master, this flag is raised to indicate

the error. Write a 0 to this bit to clear it.

SPIRxOF

SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit.

SPIRxOF

TIMODE

Result

The SPI2CRx SFR (Address 0x9B) contains valid data.

Set if the SPI2CRx SFR is not read before the end of the next byte transfer. If the RxOFW

bit (SPIMOD1, Address 0xE8[2]) is set and this condition occurs, SPI2CRx is overwritten.

SPIRxIRQ

SPI receive mode interrupt flag. Reading the SPI2CRx SFR clears this bit.

SPIRxIRQ

TIMODE

Result

The SPI2CRx SFR does not contain new data.

Set when the SPI2CRx SFR contains new data. If the SPI/I2C interrupt is enabled, an

interrupt is generated when this bit is set. If the SPI2CRx SFR is not read before the

end of the current byte transfer, the transfer stops and the SS pin is deasserted.

The SPI2CRx SFR contains new data.

SPIRxBF

Status bit for the SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx SFR clears this flag.

SPITxUF

Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx

(Address 0x9A). Write a 0 to this bit to clear it.

SPITxIRQ

SPI transmit mode interrupt flag. Writing new data to the SPI2CTx SFR clears this bit.

SPITxIRQ

TIMODE

Result

The SPI2CTx SFR is full.

The SPI2CTx SFR is empty.

Set when the SPI2CTx SFR is empty. If the SPI/I2C interrupt is enabled, an interrupt is

generated when this bit is set. If new data is not written to the SPI2CTx SFR before the

end of the current byte transfer, the transfer stops and the SS pin is deasserted.

Write a 0 to this bit to clear it.

SPITxBF

Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.

1 X = don’t care.

SPI PINS

MISO (Master In, Slave Out Data I/O Pin)

The MISO (P0.5/MISO/ZX) pin is configured as an input line

in master mode and as an output line in slave mode. The MISO

line on the master (data in) should be connected to the MISO

line in the slave device (data out). The data is transferred as

byte-wide (8-bit) serial data, MSB first.

MOSI (Master Out, Slave In Pin)

The MOSI (P0.4/MOSI/SDATA) pin is configured as an output

line in master mode and as an input line in slave mode. The MOSI

line on the master (data out) should be connected to the MOSI

line in the slave device (data in). The data is transferred as byte-

wide (8-bit) serial data, MSB first.

SCLK (Serial Clock I/O Pin)

The master serial clock (SCLK) is used to synchronize the data

being transmitted and received through the MOSI and MISO

data lines. The SCLK (P0.6/SCLK/T0) pin is configured as an

output in master mode and as an input in slave mode.

In master mode, the bit rate, polarity, and phase of the clock are

controlled by SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)

and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).

In slave mode, the SPIMOD2 SFR (Address 0xE9) must be con-

figured with the phase and polarity of the expected input clock.

In both master and slave modes, the data is transmitted on one

edge of the SCLK signal and sampled on the other. It is important,

therefore, that the SPICPOL and SPICPHA bits (SPIMOD2[3:2])

be configured the same for the master and slave devices.

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