ADE5166 datasheet(142/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 142 of 156

SS (Slave Select Pin)

In SPI slave mode, a transfer is initiated by the assertion of SS

low. The SPI port then transmits and receives 8-bit data until

the data is concluded by the deassertion of SS according to the

AUTO_SS bit setting (SPIMOD1[4]). In slave mode, SS is always

an input.

In SPI master mode, the SS (P0.7/SS/T1/RxD2) pin can be used

to control data transfer to a slave device. In the automatic slave

select control mode, the SS pin is asserted low to select the slave

device and then raised to deselect the slave device after the transfer

is complete. Automatic slave select control is enabled by setting

the AUTO_SS bit (SPIMOD1[4]).

In a multimaster system, the SS pin can be configured as an

input so that the SPI peripheral can operate as a slave in some

situations and as a master in others. In this case, the slave selects

for the slaves controlled by this SPI peripheral should be

generated with general I/O pins.

SPI MASTER OPERATING MODES

The double-buffered receive and transmit registers can be used to

maximize the throughput of the SPI peripheral by continuously

streaming out data in master mode. The continuous transmit mode

is designed to use the full capacity of the SPI. In this mode, the

master transmits and receives data until the SPI/I2C transmit

buffer SFR (SPI2CTx, Address 0x9A) is empty at the start of a byte

transfer. Continuous mode is enabled by setting the SPICONT bit

(SPIMOD2[7]). The SPI peripheral also offers a single byte read/

write function.

In master mode, the type of transfer is handled automatically,

depending on the configuration of the SPICONT bit. The

following procedures show the sequence of events that should be

performed for each master operating mode. Based on the SS

configuration, some of these events take place automatically.

Procedures for Using SPI as a Master

Single-Byte Write Mode, SPICONT (SPIMOD2[7]) = 0

Write to the SPI2CTx SFR.

SS is asserted low, and a write routine is initiated.

The SPITxIRQ interrupt flag (SPISTAT[1]) is set when the

SPI2CTx register is empty.

SS is deasserted high.

Write to the SPI2CTx SFR to clear the SPITxIRQ inter-

rupt flag.

Continuous Mode, SPICONT (SPIMOD2[7]) = 1

Write to the SPI2CTx SFR.

SS is asserted low, and a write routine is initiated.

Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR.

Transfer continues until the SPI2CTx register and transmit

shift registers are empty.

The SPITxIRQ interrupt flag is set when the SPI2CTx

SS is deasserted high.

Write to the SPI2CTx SFR to clear the SPITxIRQ inter-

rupt flag.

Figure 111 shows the SPI output for certain automatic chip select

and continuous mode selections. Note that if the continuous mode

is not used, a short delay is inserted between transfers.

SCLK

DOUT

DIN

DIN1

DIN2

AUTO_SS = 1

SPICONT = 0

SCLK

DOUT

DIN

DIN1

AUTO_SS = 1

SPICONT = 1

DIN2

AUTO_SS = 0

SPICONT = 0

(MANUAL SS CONTROL)

DOUT1

DOUT2

DOUT1

DOUT2

SCLK

DOUT

DIN

DIN1

DIN2

DOUT1

DOUT2

Figure 111. Automatic Chip Select and Continuous Mode Output

Note that reading the contents of the SPI/I2C receive buffer SFR

(SPI2CRx, Address 0x9B) should be done using a 2-cycle instruc-

tion set, such as MOV A or SPI2CRX. Using a 3-cycle instruction

set, such as MOV 0x3D or SPI2CRX, does not transfer the right

information into the target register.

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