MC68HC705P9CS datasheet(110/160 Pages) FREESCALE

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Timer

Technical Data

MC68HC705P9 — Rev. 4.0

110

Timer

MOTOROLA

Bits 4–2 — Unused

These are read/write bits that always read as logic zeros.

IEDG — Input Edge

The state of this read/write bit determines whether a positive or

negative transition on the PD7/TCAP pin triggers a transfer of the

contents of the timer registers to the input capture registers. Reset

has no effect on the IEDG bit.

1 = Positive edge (low-to-high transition) triggers input capture

0 = Negative edge (high-to-low transition) triggers input capture

OLVL — Output Level

The state of this read/write bit determines whether a logic one or a

logic zero appears on the TCMP pin when a successful output

compare occurs. Reset clears the OLVL bit.

1 = TCMP goes high on output compare

0 = TCMP goes low on output compare

9.7.2 Timer Status Register

The timer status register (TSR) contains flags for the following events:

•

An active signal on the PD7/TCAP pin, transferring the contents of

the timer registers to the input capture registers

•

A match between the 16-bit counter and the output compare

registers, transferring the OLVL bit to the TCMP pin

•

A timer rollover from $FFFF to $0000

$0013

Bit 7

54321

Bit 0

Read:

ICF

OCF

TOF

00000

Write:

Reset:

00000

= Unimplemented

U = Unaffected

Figure 9-11. Timer Status Register (TSR)

Freescale Semiconductor, Inc.

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