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OTB25LPLL 数据表(PDF) 65 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 65 Page - Actel Corporation |
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65 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 1-61 Synchronous Write and Read to the Same Location Note: The plot shows the normal operation status. Figure 1-37 • Synchronous Write and Read to the Same Location Table 1-56 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLKS ↑ to RCLKS ↑ setup time – 0.1 ns WCLKRCLKH WCLKS ↑ to RCLKS ↑ hold time 7.0 ns OCH Old DO valid from RCLKS ↑ 3.0 ns OCA/OCH displayed for Access Timed Output OCA New DO valid from RCLKS ↑ 7.5 ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. All –F speed grade devices are 20% slower than the standard numbers. * New data is read if WCLKS ↑ occurs before setup time. The data stored is read if WCLKS ↑ occurs after hold time. RCLKS DO WCLKS tWCLKRCLKH New Data* Last Cycle Data tWCLKRCLKS tOCH tCCYC tCMH tCML tOCA |
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