OTB25LPLL datasheet(19/174 Pages) ACTEL

19 / 174 page

ProASICPLUS Flash Family FPGAs

v5.2

1-15

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.

Figure 1-15 • Input Connectors to ProASICPLUS Clock Conditioning Circuitry

Table 1-7 •

Clock-Conditioning Circuitry MUX Settings

MUX

Datapath

Comments

FBSEL

Internal Feedback

Internal Feedback and Advance Clock Using FBDLY

–0.25 to –4 ns in 0.25 ns increments

External Feedback (EXTFB)

XDLYSEL

Feedback Unchanged

Deskew feedback by advancing clock by system delay

Fixed delay of -2.95 ns

OBMUX

GLB

Primary bypass, no divider

Primary bypass, use divider

Delay Clock Using FBDLY

+0.25 to +4 ns in 0.25 ns increments

Phase Shift Clock by 0°

Phase Shift Clock by +90°

Phase Shift Clock by +180°

Phase Shift Clock by +270°

OAMUX

GLA

Secondary bypass, no divider

Secondary bypass, use divider

Delay Clock Using FBDLY

+0.25 to +4 ns in 0.25 ns increments

Phase Shift Clock by 0°

Configuration Tile

PECL Pad Cell

GLMX

Std. Pad Cell

NPECL

PPECL

CORE

Package Pins

Physical I/O

Buffers

Global MUX

External

Feedback

Global MUX B

OUT

Global MUX A

OUT

Legend

Physical Pin

DATA Signals to the Core

DATA Signals to the PLL Block

DATA Signals to the Global MUX

Control Signals to the Global MUX

OTB25LPLL 数据表(PDF) 19 Page - Actel Corporation

OTB25LPLL 数据表(HTML) 19 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载