OTB25LPLL datasheet(53/174 Pages) ACTEL

53 / 174 page

ProASICPLUS Flash Family FPGAs

v5.2

1-49

Table 1-39 • Worst-Case Military Conditions

VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Macro Type

Description

Max. tINYH

Max. tINYL

Std.

GL33

3.3V, CMOS Input Levels3, No Pull-up Resistor

1.1

GL33S

3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger

1.1

PECL

PPECL Input Levels

1.1

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3V for delays.

Table 1-40 • Worst-Case Military Conditions

VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Macro Type

Description

Max. tINYH

Max. tINYL

Std.

GL25LP

2.5V, CMOS Input Levels3, Low Power

1.0

1.1

GL25LPS

2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger

1.4

1.0

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3V for delays.

OTB25LPLL 数据表(PDF) 53 Page - Actel Corporation

OTB25LPLL 数据表(HTML) 53 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载