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OTB25LPLL 数据表(PDF) 23 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 23 Page - Actel Corporation |
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23 / 174 page ![]() ProASICPLUS Flash Family FPGAs v5.2 1-19 Figure 1-20 • Using the PLL for Clock Deskewing ÷u ÷v ÷n ÷m D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GL B GL A 133 MHz 133 MHz /1 /1 D Q Q SET CLR Off chip On chip Reference clock 270˚ 180˚ 90˚ 0˚ |
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