OTB25LPLL datasheet(56/174 Pages) ACTEL

56 / 174 page

ProASICPLUS Flash Family FPGAs

1- 52

v5.2

Table 1-46 • Recommended Operating Conditions

Parameter

Symbol

Limits

Commercial/Industrial

Military/MIL-STD-883

Maximum Clock Frequency*

fCLOCK

180 MHz

Maximum RAM Frequency*

fRAM

150 MHz

Maximum Rise/Fall Time on Inputs*

•

Schmitt Trigger Mode (10% to 90%)

•

Non-Schmitt Trigger Mode (10% to

90%)

tR/tF

N/A

100 ns

10 ns

Maximum LVPECL Frequency*

180 MHz

Maximum TCK Frequency (JTAG)

fTCK

10 MHz

Note: *All –F parts will be 20% slower than standard commercial devices.

Table 1-47 • Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C

Type

Trig. Level

Rising Edge (ns)

Slew Rate (V/ns)

Falling Edge (ns)

Slew Rate (V/ns)

PCI Mode

OB33PH

10%-90%

1.60

1.65

1.60

Yes

OB33PN

10%-90%

1.57

1.68

3.32

0.80

OB33PL

10%-90%

1.57

1.68

1.99

1.32

OB33LH

10%-90%

3.80

0.70

4.84

0.55

OB33LN

10%-90%

4.19

0.63

3.37

0.78

OB33LL

10%-90%

5.49

0.48

2.98

0.89

OB25LPHH

10%-90%

1.55

1.29

1.56

1.28

OB25LPHN

10%-90%

1.70

1.18

2.08

0.96

OB25LPHL

10%-90%

1.97

1.02

2.09

0.96

OB25LPLH

10%-90%

3.57

0.56

3.93

0.51

OB25LPLN

10%-90%

4.65

0.43

3.28

0.61

OB25LPLL

10%-90%

5.52

0.36

3.44

0.58

Notes:

1. Standard and –F parts.

2. All –F only available as commercial.

OTB25LPLL 数据表(PDF) 56 Page - Actel Corporation

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