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OTB25LPLL 数据表(PDF) 15 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 15 Page - Actel Corporation |
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15 / 174 page ![]() ProASICPLUS Flash Family FPGAs v5.2 1-11 Boundary Scan (JTAG) ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 1-12). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 1-6). Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 k Ω pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 1-13 on page 1-12. The ’1’s and ‘0’s represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASICPLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. If boundary-scan functionality is required prior to programming, refer to online technical support on the Actel website and search for ProASICPLUS BSDL. Figure 1-12 • ProASICPLUS JTAG Boundary Scan Test Logic Circuit Device Logic I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Bypass Register Instruction Register TAP Controller Test Data Registers Table 1-6 • Boundary-Scan Opcodes Hex Opcode EXTEST 00 SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF |
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