OTB25LPLL datasheet(18/174 Pages) ACTEL

18 / 174 page

ProASICPLUS Flash Family FPGAs

1- 14

v5.2

enable the user to define a wide range of frequency

multipliers and divisors. The clock conditioning circuit can

advance or delay the clock up to 8 ns (in increments of

0.25 ns) relative to the positive edge of the incoming

reference clock. The system also allows for the selection of

output frequency clock phases of 0°, 90°, 180°, and 270°.

Prior to the application of signals to the rib drivers, they

pass through programmable delay units, one per global

network. These units permit the delaying of global

signals relative to other signals to assist in the control of

input set-up times. Not all possible combinations of input

and output modes can be used. The degrees of freedom

available in the bidirectional global pad system and in

the clock conditioning circuit have been restricted. This

avoids unnecessary and unwieldy design kit and software

work.

Notes:

1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.

2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns.

3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.

Figure 1-14 • PLL Block – Top-Level View and Detailed PLL Block Diagram

AVDD

AGND

GND

VDD

External Feedback Signal

GLA

GLB

Dynamic

Configuration Bits

Flash

Configuration Bits

Clock Conditioning

Circuitry

(Top level view)

Global MUX A OUT

Global MUX B OUT

See Figure 1-15

on page 1-14

Input Pins to the PLL

GLB

GLA

÷u

÷v

PLL Core

0˚

90˚

180˚

270˚

Delay Line 0.0 ns, 0.25 ns,

0.50 ns and 4.00 ns

P+

P-

Clock from Core

(GLINT mode)

CLK

Deskew

Delay

2.95 ns

Delay Line

0.25 ns to

4.00 ns,

16 steps,

0.25 ns

increments

Delay Line 0.0 ns, 0.25 ns,

0.50 ns and 4.00 ns

Clock from Core

(GLINT mode)

CLKA

EXTFB

XDLYSEL

Bypass Secondary

Bypass Primary

FIVDIV[4:0]

FBDIV[5:0]

FBSEL[1:0]

OAMUX[1:0]

DLYA[1:0]

DLYB[1:0]

OBDIV[1:0]

OBMUX[2:0]

OADIV[1:0]

FBDLY[3:0]

÷n

÷m

Clock Conditioning Circuitry Detailed Block Diagram

OTB25LPLL 数据表(PDF) 18 Page - Actel Corporation

OTB25LPLL 数据表(HTML) 18 Page - Actel Corporation

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