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OTB25LPLL 数据表(PDF) 30 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 30 Page - Actel Corporation |
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30 / 174 page ![]() ProASICPLUS Flash Family FPGAs 1- 26 v5.2 Figure 1-23 • APA1000 Memory Block Architecture Figure 1-24 • Example Showing Memory Arrays with Different Widths and Depths Figure 1-25 • Multi-Port Memory Usage Word Depth Word Width 88 blocks 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 Word Depth Word Width 1,024 words x 9 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 words x 18 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 256 256 256 256 9 256 256 9 9 256 99 256 256 256 256 256 99 9 256 9 512 words x 9 bits, 4 read, 1 write 256 words x 9 bits, 2 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Word Depth Word Width Write Port Write Port Read Ports 9 9 Read Ports 99 9 9 256 256 256 256 256 256 256 |
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