OTB25LPLL datasheet(12/174 Pages) ACTEL

12 / 174 page

ProASICPLUS Flash Family FPGAs

1- 8

v5.2

Array Coordinates

During many place-and-route operations in Actel’s

Designer software tool, it is possible to set constraints

that require array coordinates.

Table 1-2 is provided as a reference. The array coordinates

are measured from the lower left (0,0). They can be used in

region constraints for specific groups of core cells, I/Os, and

RAM blocks. Wild cards are also allowed.

I/O and cell coordinates are used for placement

constraints. Two coordinate systems are needed because

there is not a one-to-one correspondence between I/O

cells and core cells. In addition, the I/O coordinate system

changes depending on the die/package combination.

Core cell coordinates start at the lower left corner

(represented as (1,1)) or at (1,5) if memory blocks are

present at the bottom. Memory coordinates use the

same system and are indicated in Table 1-2. The memory

coordinates for an APA1000 are illustrated in Figure 1-8.

For more information on how to use constraints, see the

Designer User’s Guide or online help for ProASICPLUS

software tools.

Table 1-2 •

Array Coordinates

Device

Logic Tile

Memory Rows

All

Min.

Max.

Bottom

Top

Min.

Max.

APA075

–

(33,33) or (33, 35)

0,0

97, 37

APA150

128

–

(49,49) or (49, 51)

0,0

129, 53

APA300

128

(1,1) or (1,3)

(69,69) or (69, 71)

0,0

129, 73

APA450

192

(1,1) or (1,3)

(69,69) or (69, 71)

0,0

193, 73

APA600

224

100

(1,1) or (1,3)

(101,101) or (101, 103)

0,0

225, 105

APA750

256

132

(1,1) or (1,3)

(133,133) or (133, 135)

0,0

257, 137

APA1000

352

164

(1,1) or (1,3)

(165,165) or (165, 167)

0,0

353, 169

Figure 1-8 • Core Cell Coordinates for the APA1000

(353,169)

(352,167)

(352,165)

(352,164)

(352,5)

(352,3)

(353,0)

(352,1)

(1,5)

(1,1)

(1,164)

(1,165)

(1,3)

(1,167)

(1,169)

(0,0)

Core

Memory

Blocks

Memory

Blocks

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