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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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OTB25LPLL 数据表(PDF) 71 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 71 Page - Actel Corporation |
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71 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 1-67 Asynchronous FIFO Read Note: The plot shows the normal operation status. Figure 1-43 • Asynchronous FIFO Read Table 1-61 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ERDH, FRDH, THRDH Old EMPTY, FULL, EQTH, & GETH valid hold time from RB ↑ 0.5 ns Empty/full/thresh are invalid from the end of hold until the new access is complete ERDA New EMPTY access from RB ↑ 3.01 ns FRDA FULL ↓ access from RB ↑ 3.01 ns ORDA New DO access from RB ↓ 7.5 ns ORDH Old DO valid from RB ↓ 3.0 ns RDCYC Read cycle time 7.5 ns RDWRS WB ↑, clearing EMPTY, setup to RB ↓ 3.02 ns Enabling the read operation 1.0 ns Inhibiting the read operation RDH RB high phase 3.0 ns Inactive RDL RB low phase 3.0 ns Active RPRDA New RPE access from RB ↓ 9.5 ns RPRDH Old RPE valid from RB ↓ 4.0 ns THRDA EQTH or GETH access from RB ↑ 4.5 ns Notes: 1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns. 3. All –F speed grade devices are 20% slower than the standard numbers. RB = (RDB+RBLKB) RPE RDATA EMPTY EQTH, GETH FULL (Empty inhibits read) Cycle Start WB tRDWRS tERDH, tFRDH tERDA, tFRDA tTHRDH tORDH tRPRDH tORDA tRPRDA tRDL tRDH tRPRDA tRDL tRDCYC tRDH tTHRDA |
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