OTB25LPLL datasheet(24/174 Pages) ACTEL

24 / 174 page

ProASICPLUS Flash Family FPGAs

1- 20

v5.2

Logic Tile Timing Characteristics

Timing characteristics for ProASICPLUS devices fall into

three categories: family dependent, device dependent,

and design dependent. The input and output buffer

characteristics are common to all ProASICPLUS family

members. Internal routing delays are device dependent.

Design dependency means that actual delays are not

determined until after placement and routing of the

user’s design are complete. Delay values may then be

determined by using the Timer utility or by performing

simulation with post-layout delays.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most

timing-critical paths. Critical nets are determined by net

property assignment prior to place-and-route. Refer to

the Actel Designer User’s Guide or online help for details

on using constraints.

Timing Derating

Since ProASICPLUS devices are manufactured with a

CMOS process, device performance will vary with

temperature, voltage, and process. Minimum timing

parameters

reflect

maximum

operating

voltage,

minimum operating temperature, and optimal process

variations. Maximum timing parameters reflect minimum

operating voltage, maximum operating temperature,

and

worst-case

process

variations

(within

process

specifications). The derating factors shown in Table 1-9

should be applied to all timing data contained within

this datasheet.

All timing numbers listed in this datasheet represent

sample timing characteristics of ProASICPLUS devices.

Actual timing delay values are design-specific and can be

derived from the Timer tool in Actel’s Designer software

after place-and-route.

Table 1-9 •

Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, TJ = 70°C, VDD = 2.3 V)

–55°C

–40°C

0°C

25°C

70°C

85°C

110°C

125°C

135°C

150°C

2.3 V

0.84

0.860.910.941.001.021.05

1.13

1.181.27

2.5 V

0.81

0.820.870.900.950.981.01

1.09

1.131.21

2.7 V

0.77

0.790.830.860.910.930.96

1.04

1.081.16

Notes:

1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 175°C.

2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.

OTB25LPLL 数据表(PDF) 24 Page - Actel Corporation

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