OTB25LPLL datasheet(52/174 Pages) ACTEL

52 / 174 page

ProASICPLUS Flash Family FPGAs

1- 48

v5.2

Global Input Buffer Delays

Table 1-37 • Worst-Case Commercial Conditions

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Macro Type

Description

Max. tINYH

Max. tINYL

Units

Std.3

–F

Std.3

–F

GL33

3.3 V, CMOS Input Levels4, No Pull-up Resistor

1.0

1.2

1.1

1.3

GL33S

3.3 V, CMOS Input Levels4, No Pull-up Resistor, Schmitt Trigger

1.0

1.2

1.1

1.3

PECL

PPECL Input Levels

1.0

1.2

1.1

1.3

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. Applies to Military ProASICPLUS devices.

4. LVTTL delays are the same as CMOS delays.

5. For LP Macros, VDDP=2.3 V for delays.

6. All –F parts are only available as commercial.

Table 1-38 • Worst-Case Commercial Conditions

VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C

Macro Type

Description

Max. tINYH

Max. tINYL

Units

Std.3

–F

Std.3

–F

GL25LP

2.5 V, CMOS Input Levels4, Low Power

1.1

1.2

1.0

1.3

GL25LPS

2.5 V, CMOS Input Levels4, Low Power, Schmitt Trigger

1.3

1.6

1.0

1.1

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. Applies to Military ProASICPLUS devices.

4. LVTTL delays are the same as CMOS delays.

5. For LP Macros, VDDP=2.3 V for delays.

6. All –F parts are only available as commercial.

OTB25LPLL 数据表(PDF) 52 Page - Actel Corporation

OTB25LPLL 数据表(HTML) 52 Page - Actel Corporation

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OTB25LPLL 数据表(PDF) 52 Page - Actel Corporation

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