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OTB25LPLL 数据表(PDF) 28 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 28 Page - Actel Corporation |
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28 / 174 page  ProASICPLUS Flash Family FPGAs 1- 24 v5.2 Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-21 • Example SRAM Block Diagrams Table 1-13 • Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 In Write clock used on synchronization on write side RCLKS 1 In Read clock used on synchronization on read side RADDR<0:7> 8 In Read address RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) WADDR<0:7> 8 In Write address WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> can be used for parity In WRB 1 In Write pulse (active Low) DO<0:8> 9 Out Output data bits <0:8>, <8> can be used for parity Out RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) PARODD 1 In Selects Odd parity generation/detect when High, Even parity when Low Note: Not all signals shown are used in all modes. SRAM (256x9) DI <0:8> DO <0:8> RADDR <0:7> WADDR <0:7> WRB RDB WBLKB RBLKB WCLKS RCLKS RPE PARODD DI <0:8> WADDR <0:7> WRB WBLKB PARODD WPE WPE SRAM (256x9) DI <0:8> DO <0:8> WADDR <0:7> WRB RDB WBLKB RBLKB WCLKS RPE PARODD WPE RADDR <0:7> PARODD DI <0:8> DO <0:8> RADDR <0:7> WADDR <0:7> WRB RDB WBLKB RBLKB RCLKS RPE WPE DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE Sync Write and Sync Read Ports Async Write and Async Read Ports Sync Write and Async Read Ports Async Write and Sync Read Ports SRAM (256x9) SRAM (256x9) |
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