| 数据搜索系统,热门电子元器件搜索 |
|
OTB25LPLL 数据表(PDF) 14 Page - Actel Corporation |
|
|
|||||||||||||||||||||||||||||
OTB25LPLL 数据表(HTML) 14 Page - Actel Corporation |
|
14 / 174 page ![]() ProASICPLUS Flash Family FPGAs 1- 10 v5.2 Power-Up Sequencing While ProASICPLUS devices are live at power-up, the order of VDD and VDDP power-up is important during system start-up. VDD should be powered up simultaneously with VDDP on ProASIC PLUS devices. Failure to follow these guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel’s Power-Up Behavior of ProASICPLUS Devices application note. LVPECL Input Pads In addition to standard I/O pads and power pads, ProASICPLUS devices have a single LVPECL input pad on both the east and west sides of the device, along with AVDD and AGND pins to power the PLL block. The LVPECL pad cell consists of an input buffer (containing a low voltage differential amplifier) and a signal and its complement, PPECL (I/P) (PECLN) and NPECL (PECLREF). The LVPECL input pad cell differs from the standard I/O cell in that it is operated from VDD only. Since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. As a special high-speed differential input, it also does not require pull ups. Recommended termination for LVPECL inputs is shown in Figure 1-10. The LVPECL pad cell compares voltages on the PPECL (I/P) pad (as illustrated in Figure 1-11) and the NPECL pad and sends the results to the global MUX (Figure 1-14 on page 1-14). This high-speed, low-skew output essentially controls the clock conditioning circuit. LVPECLs are designed to meet LVPECL JEDEC receiver standard levels (Table 1-5). Figure 1-10 • Recommended Termination for LVPECL Inputs Figure 1-11 • LVPECL High and Low Threshold Values Table 1-5 • LVPECL Receiver Specifications Symbol Parameter Min. Max Units VIH Input High Voltage 1.49 2.72 V VIL Input Low Voltage 0.86 2.125 V VID Differential Input Voltage 0.3 VDD V + _ PPECL NPECL From LVPECL Driver Data Z = 50 Ω 0 Z = 50 Ω 0 R = 100 Ω 2.72 2.125 1.49 0.86 Voltage |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |