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OTB25LPLL 数据表(PDF) 55 Page - Actel Corporation

部件名 OTB25LPLL
功能描述  Ultra-Fast Local and Long-Line Network
PDF  174 Pages
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制造商  ACTEL [Actel Corporation]
网页  http://www.actel.com
标志 ACTEL - Actel Corporation

OTB25LPLL 数据表(HTML) 55 Page - Actel Corporation

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ProASICPLUS Flash Family FPGAs
v5.2
1-51
Module Delays
Sample Macrocell Library Listing
Figure 1-29 • Module Delays
Table 1-45 • Worst-Case Military Conditions1
VDD = 2.3 V, TJ = 70º C, TJ = 70°C, TJ = 125°C for Military/MIL-STD-883
Cell Name
Description
Std.
–F2
Max
Min
Max
Min
Units
NAND2
2-Input NAND
0.5
0.6
ns
AND2
2-Input AND
0.7
0.8
ns
NOR3
3-Input NOR
0.8
1.0
ns
MUX2L
2-1 MUX with Active Low Select
0.5
0.6
ns
OA21
2-Input OR into a 2-Input AND
0.8
1.0
ns
XOR2
2-Input Exclusive OR
0.6
0.8
ns
LDL
Active Low Latch (LH/HL)
LH3
0.9
1.1
ns
CLK-Q
HL3
0.8
0.9
ns
tsetup
0.7
0.8
ns
thold
0.1
0.2
ns
DFFL
Negative Edge-Triggered D-type Flip-Flop (LH/HL)
CLK-Q
LH3
0.9
1.1
ns
HL3
0.8
1.0
ns
tsetup
0.6
0.7
ns
thold
0.0
0.0
ns
Notes:
1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of
local interconnect.
2. All –F parts are only available as commercial.
3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.
A
B
50%
Y
50%
50% 50%
50%
50%
DALH
C
50%50%
50%
50%
50%
DBLH
DAHL
DBHL
DCHL
DCLH
50%
t
t
t
t
t
t
A
B
C
Y



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