OTB25LPLL datasheet(67/174 Pages) ACTEL

67 / 174 page

ProASICPLUS Flash Family FPGAs

v5.2

1-63

Asynchronous Write and Read to the Same Location

Note: The plot shows the normal operation status.

Figure 1-39 • Asynchronous Write and Read to the Same Location

Table 1-58 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

ORDA

New DO access from RB

↓

7.5

ORDH

Old DO valid from RB

↓

3.0

OWRA

New DO access from WB

↑

3.0

OWRH

Old DO valid from WB

↑

0.5

RAWRS

↓ or RADDR from WB ↓

5.0

RAWRH

↑ or RADDR from WB ↑

5.0

Notes:

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more

information.

2. Violation or RAWRS will disturb access to the OLD data.

3. Violation of RAWRH will disturb access to the NEWER data.

4. All –F speed grade devices are 20% slower than the standard numbers.

RB, RADDR

OLD

NEWER

NEW

tORDA

tORDH

tOWRH

tRAWRH

WB = {WRB+WBLKB}

tOWRA

tRAWRS

OTB25LPLL 数据表(PDF) 67 Page - Actel Corporation

OTB25LPLL 数据表(HTML) 67 Page - Actel Corporation

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