OTB25LPLL datasheet(44/174 Pages) ACTEL

44 / 174 page

ProASICPLUS Flash Family FPGAs

1- 40

v5.2

Table 1-23 • DC Specifications (3.3 V PCI Operation)1

Symbol

Parameter

Condition

Commercial/

Industrial2,3

Military/MIL-STD- 8832,3

Units

Min.

Max.

Min.

Max.

VDD

Supply Voltage for Core

2.3

2.7

2.3

2.7

VDDP

Supply Voltage for I/O Ring

3.0

3.6

3.0

3.6

VIH

Input High Voltage

0.5VDDP VDDP + 0.5

0.5VDDP

VDDP + 0.5

VIL

Input Low Voltage

–0.5

0.3VDDP

–0.5

0.3VDDP

IIPU

Input Pull-up Voltage4

0.7VDDP

IIL

Input Leakage Current5

0 < VIN < VDDP

Std.

–10

–50

µA

–F3, 6

–10

100

µA

VOH

Output High Voltage

IOUT = –500 µA

0.9VDDP

VOL

Output Low Voltage

IOUT = 1500 µA

0.1VDDP

CIN

Input Pin Capacitance (except CLK)

CCLK

CLK Pin Capacitance

Notes:

1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.

2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military.

3. All –F parts are available as commercial only.

4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated

network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum

current at this input voltage.

5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.

OTB25LPLL 数据表(PDF) 44 Page - Actel Corporation

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