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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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OTB25LPLL 数据表(PDF) 61 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 61 Page - Actel Corporation |
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61 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 1-57 Asynchronous SRAM Write Note: The plot shows the normal operation status. Figure 1-33 • Asynchronous SRAM Write Table 1-52 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx Description Min. Max. Units Notes AWRH WADDR hold from WB ↑ 1.0 ns AWRS WADDR setup to WB ↓ 0.5 ns DWRH DI hold from WB ↑ 1.5 ns DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive. DWRS DI setup to WB ↑ 2.5 ns PARGEN is active. WPDA WPE access from DI 3.0 ns WPE is invalid, while PARGEN is active. WPDH WPE hold from DI 1.0 ns WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WRML WB low phase 3.0 ns Active Note: All –F speed grade devices are 20% slower than the standard numbers. WRB, WBLKB WADDR WPE DI tAWRS tWPDA tAWRH tDWRS tWRML tWRMH tWRCYC tWPDH tDWRH |
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