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OTB25LPLL 数据表(PDF) 26 Page - Actel Corporation |
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OTB25LPLL 数据表(HTML) 26 Page - Actel Corporation |
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26 / 174 page  ProASICPLUS Flash Family FPGAs 1- 22 v5.2 User Security ProASICPLUS devices have FlashLock protection bits that, once programmed, block the entire programmed contents from being read externally. Please refer to Table 1-10 for details on the number of bits in the key for each device. If locked, the user can only reprogram the device employing the user-defined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (actually very small capacitors) rather than in the wiring, physical deconstruction cannot be used to compromise data. This type of security breach is further discouraged by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel’s Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. Embedded Memory Floorplan The embedded memory is located across the top and bottom of the device in 256x9 blocks (Figure 1-1 on page 1-2). Depending on the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory array or combined (using dedicated memory routing resources) to form larger, more complex memory configurations. A single memory configuration could include blocks from both the top and bottom memory locations. Embedded Memory Configurations The embedded memory in the ProASICPLUS family provides great configuration flexibility (Table 1-11). Each ProASICPLUS block is designed and optimized as a two- port memory (one read, one write). This provides 198 kbits of two-port and/or single port memory in the APA1000 device. Each memory block can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 1-12). Additional characteristics include programmable flags as well as parity checking and generation. Figure 1-21 on page 1-24 and Figure 1-22 on page 1-25 show the block diagrams of the basic SRAM and FIFO blocks. Table 1-13 on page 1-24 and Table 1-14 on page 1-25 describe memory block SRAM and FIFO interface signals, respectively. A single memory block is designed to operate at up to 150 MHz (standard speed grade typical conditions). Each block is comprised of 256 9-bit words (one read port, one write port). The memory blocks may be cascaded in width and/or depth to create the desired memory organization. (Figure 1-23 on page 1-26). This provides optimal bit widths of 9 (one block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel’s ACTgen User’s Guide for more information. Figure 1-24 on page 1-26 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three arrays of various widths and depths. Figure 1-25 on page 1-26 shows how RAM blocks can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port RAM. The Actel ACTgen software facilitates building wider and deeper memory configurations for optimal memory usage. Table 1-10 • Flashlock Key Size by Device Device Key Size APA075 79 bits APA150 79 bits APA300 79 bits APA450 119 bits APA600 167 bits APA750 191 bits APA1000 263 bits ® Table 1-11 • ProASICPLUS Memory Configurations by Device Device Bottom Top Maximum Width Maximum Depth DWDW APA075 0 12 256 108 1,536 9 APA150 0 16 256 144 2,048 9 APA300 16 16 256 144 2,048 9 APA450 24 24 256 216 3,072 9 APA600 28 28 256 252 3,584 9 APA750 32 32 256 288 4,096 9 APA1000 44 44 256 396 5,632 9 |
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