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4-1

4 – Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Revision

Changes

Page

Revision 18

(March 2012)

Table 2-1 • Absolute Maximum Ratings was updated to correct the maximum

DC core supply voltage (VCCA) from 1.6 V to 1.7 V (SAR 36786). The

maximum input voltage (VI) was corrected from 3.75 V to 4.1 V (SAR 35419).

2-1

Values for tristate leakage current IOZ, and IIH and IIL were added to Table 2-3

• Standby Current (SARs 35774, 32021).

2-2

Figure 2-2 • VCCPLX and VCOMPLX Power Supply Connect was updated to

correct the units for the resistance from "W" to

Ω (SAR 36415).

2-9

In the Introduction to the "User I/Os" section, the following sentence was added

to clarify the slew rate setting (SAR 34943):

The slew rate setting is effective for both rising and falling edges.

2-11

Figure 2-3 • Use of an External Resistor for 5 V Tolerance was revised to show

the VCCI and GND clamp diodes. The explanatory text above the figure was

revised as well (SAR 34942).

2-13

EQ 3 for 5 V tolerance was corrected to change Vdiode from 0.6 V to 0.7 V

(SAR 36786).

2-13

Additional information was added to the "Using the Weak Pull-Up and Pull-Down

Circuits" section to clarify how the weak pull-up and pull-down resistors are

physically implemented (SAR 34945).

2-17

The description for the CINCLK parameter in Table 2-18 • Input Capacitance was

changed from "Input capacitance on clock pin" to "Input capacitance on HCLK

and RCLK pin" (SAR 34944).

2-21

Table 2-19 • I/O Input Rise Time and Fall Time* is new (SAR 34942).

2-21

The minimum VIL for 1.5 V LVCMOS and PCI was corrected from –0.5 to –0.3 in

Table 2-29 • DC Input and Output Levels and Table 2-33 • DC Input and Output

Levels (SAR 34358).

2-38, 2-40

Support for simulating the GCLR/ GPSET feature in the Axcelerator Family was

added in Libero software v9.0 SPI1. Reference to the section explaining this in

the Antifuse Macro Library Guide was added to the "R-Cell" section (SAR

26413).

2-58

The enable signal in Figure 2-32 • R-Cell Delays was corrected to show it is

active low rather than active high (SAR 34946).

2-59

Revision 17

(September 2011)

The versioning system for datasheets has been changed. Datasheets are

assigned a revision number that increments each time the datasheet is revised.

The "Axcelerator Family Device Status" table indicates the status for each

device in the device family.

iii

The "Features" section, "Programmable Interconnect Element" section, and

"Security" section were revised to clarify that although no existing security

measures can give an absolute guarantee, Microsemi FPGAs implement the

best security available in the industry (SAR 32865).

i, 1-1, 2-108

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