AX2000 datasheet(257/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

4-3

Revision 12

(v2.4)

Revised ordering information and timing data to reflect phase out of –3 speed

grade options.

Table 2-3 was updated.

Revision 11

(v2.3)

The "Packaging Data" section is new.

Table 2-2 was updated.

2-1

"VCCDA Supply Voltage" was updated.

2-9

"PRA/B/C/D Probe A, B, C and D" was updated.

2-10

The "User I/Os" was updated.

2-11

Revision 10

(v2.2)

Figure 1-3 was updated.

1-2

Table 2-2 was updated.

2-1

The "Power-Up/Down Sequence" section was updated.

2-1

Table 2-4 was updated.

2-3

Table 2-5 was updated.

2-4

The "Timing Characteristics" section was added.

2-7

Table 2-7 was updated.

2-7

Figure 2-1 was updated.

2-8

The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired

Clock – Using LVTTL 24 mA High Slew Clock I/O" section were updated.

2-8

The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock – Using

LVTTL 24 mA High Slew Clock I/O" section were updated.

2-8

The "Global Pins" section was updated.

2-10

The "User I/Os" section was updated.

2-11

Table 2-17 was updated.

2-19

Figure 2-8 was updated.

2-20

Figure 2-13 and Figure 2-14 were updated.

2-24

The following timing parameters were renamed in I/O timing characteristic

tables from Table 2-22 to Table 2-60:

tIOCLKQ > tICLKQ

tIOCLKY > tOCLKQ

2-26 to 2-52

Timing numbers were updated from Table 2-22 to Table 2-78.

2-26 to 2-69

The "R-Cell" section was updated.

2-58

Figure 2-59 was updated.

2-89

Figure 2-60 was updated.

2-89

Figure 2-67 was updated.

2-100

Figure 2-68 was updated.

2-101

Table 2-89 to Table 2-93 were updated.

2-90 to 2-94

Table 2-98 to Table 2-102 were updated.

2-102 to

2-106

Revision

Changes

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