RM0319 datasheet(64/368 Pages) STMICROELECTRONICS

64 / 368 page

Multiport DDR controller (MPMC)

RM0319

64/368

Doc ID 022640 Rev 3

Early burst termination

Unlike the AHB bus protocol, the MPMC core bus protocol does not allow early burst

termination. As a result, the core requires the master to complete the whole READ/WRITE

Table 18.

AHB-Memory controller translation example

AHBx transaction

Memory controller transaction

Address

Burst size

AHBx

HBURST

Bytes per beat

(AHBx HSIZE)

Address

Length

AHBx

Address

SINGLE

Byte, half-word or

word

AHBx Address

1 x (AHBx HSIZE)

AHBx

Address

INCR4

Byte, half-word or

word

AHBx Address

4 x (AHBx HSIZE)

AHBx

Address

INCR8

Byte, half-word or

word

AHBx Address

8 x (AHBx HSIZE)

AHBx

Address

INCR16

Byte, half-word or

word

AHBx Address

16 x (AHBx HSIZE)

AHBx

Address

WRAP4

(offset n= 0-3)

Byte, half-word or

word

Transaction#1:

AHBx Address

Transaction #2:

Wrapped AHBx Address

Transaction #1:

(4 - n) x (AHBx

HSIZE)

Transaction #2:

n x (AHBx HSIZE)

AHBx

Address

WRAP8

(offset n= 0-7)

Byte, half-word or

word

Transaction#1:

AHBx Address

Transaction #2:

Wrapped AHBx Address

Transaction #1:

(8 - n) x (AHBx

HSIZE)

Transaction #2:

n x (AHBx HSIZE)

AHBx

Address

WRAP16

(offset n= 0-

15)

Byte, half-word or

word

Transaction#1:

AHBx Address

Transaction #2:

Wrapped AHBx Address

Transaction #1:

(16 - n) x (AHBx

HSIZE)

Transaction #2:

n x (AHBx HSIZE)

AHBx

Address

INCR

(for each

beat)

Byte or half-word

AHBx Address

1 x (AHBx HSIZE)

AHBx

Address

INCR

Word

Transaction 1:

AHBx HADDR

Transaction 2:

AHBx HADDR+blk size

Transaction 3:

2 x (AHBx HADDR+blk

size)(1)

blk size is the value in ahbX_rdnct or abhX_wrcnt.

(AHBx read_cnt)

(AHBx write_cnt)(2)

Programmable value

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