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RM0319 数据表(PDF) 75 Page - STMicroelectronics |
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RM0319 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 368 page  RM0319 Multiport DDR controller (MPMC) Doc ID 022640 Rev 3 75/368 command will be arbitrated first and the higher priority command afterward. This situation could modify the arbitration latency slightly, causing it to be longer than the expected value in the priority relax parameter. Consider the System F as described in Table 26. The same conditions apply as for the previous example. The command queue is considered to never be full, commands from ports 0, 1, 2 and 3 are only received at priority level 0, and commands from ports 4 and 5 are only received at priority 1. Table 27 shows the system behavior. The exact settings of the latency control and priority relax parameters are not displayed. Relaxed Ports column indicates instead which ports, if any, have hit their priority relax values. The following cycles are important to observe: ● Cycles 1 and 7: A port relaxes while a higher priority request and a higher scan order request are both present. The relaxed port still wins arbitration. ● Cycle 4: Two ports of the same priority relax. The higher scan order request wins arbitration. ● Cycle 5: Two ports of different priorities relax. The lower priority port that relaxed wins arbitration. The higher priority port that relaxed will maintain its relax condition, and win arbitration in the next cycle. Table 26. System F specifications Parameter Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 ahbX_priority0_relative_priority 4 3 2 1 1 1 ahbX_priority1_relative_priority 1 1 1 1 2 1 ahbX_port_ordering 0 1 2 3 5 4 Table 27. System F operation with priority relaxing Cycle Ports Requesting Relaxed Ports Arbitration Winner Next Counter Next Scan Order P 0 P 1 P 2 P 3 P 4 P 5 P 0 P 1 P 2 P 3 P 4 P 5 Priority 0: P0-P1-P2- P3 Priority 1: P5-P4 0 Y Y Y P2 001 000 P0-P1-P2-P3 P5-P4 1 Y Y Y P5 P5 001 001 P0-P1-P2-P3 P5-P4 2 Y Y Y P2 002 000 P0-P1-P3-P2 P4-P5 3 Y Y Y P1 010 000 P0-P1-P3-P2 P4-P5 4 Y Y Y P4, P5 P4 0 1 0 0 1 0 P0-P1-P3-P2 P4-P5 5 Y Y Y P0, P5 P5 0 1 0 0 1 1 P0-P1-P3-P2 P4-P5 |
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