RM0319 datasheet(86/368 Pages) STMICROELECTRONICS

86 / 368 page

Multiport DDR controller (MPMC)

RM0319

86/368

Doc ID 022640 Rev 3

automatic entry option is chosen. The counters are also shown in Table 30. Since the two

power-down modes share one counter, wishing the user automatically enter Memory Power-

Down mode (Mode 1), the Memory Power-Down with Memory Clock Gating mode (Mode 2)

must not be enabled.

Controller clock gating and re-locking

When the memory controller is in its deepest low power modes, the clock to the memory

controller is gated off, except for a small portion of the DLL to maintain the current

frequency. Since the voltage and temperature differences of the chip can change and the

DLL would not adjust to these changes, it is possible that the memory controller DLL shifts

out of range of the controller clock.

The DLL can respond to slight variations of the frequency very quickly, but it requires a long

time to manage large shifts. Therefore, it is better the memory controller to be periodically

awoken from controller clock gating, so it can resynchronize to the controller clock and then

resume controller clock gating.

The interval among synchronizations is user-defined by the lowpoxer_rfsh_hold parameter.

This value directly feeds a counter and sets the number of cycles that the memory controller

will wait before attempting to re-lock the DLL.

Note:

This is only relevant when the controller clock is gated (Mode 5).

When this counter expires, the DLL will be un-gated and the DLL will attempt to re-lock. The

clock will be kept un-gated for at least 16 cycles, even if the DLL locks during that time. Once

the DLL has re-locked and the 16 cycles have elapsed, the DLL controller clock will be gated

again and the counter will restart countdown at the value in the lowpoxer_rfsh_hold

parameter.

Refresh masking

Regular refresh commands will be issued at the same intervals as the memory controller is

operating normally, is idle, or is in any of the low power modes. However, for memory arrays

with multiple chip selects, the memory controller can mask refreshes during any of the low

power modes. By setting bits of the lowpower_refresh_enable parameter to 1'b1, auto-

refreshes will be masked for the associated chip selects.

The user should ensure that refreshes are not constantly masked, and that each chip select

is refreshed periodically.

6.4.4

Low power and clock forwarding

The memory controller implements a clock forwarding scheme, which eliminates the need

for a de-skew PLL and reduces the overall power consumption of the device. Controllers that

are configured for low power should also be configured for clock forwarding.

6.4.5

Mobile DDR/SDRAM devices

Enabling mobile usage

When the device is used inside a mobile device, the parameter en_lowpower_mode must be

set to 1'b1. This enables the memory controller to use the initialization sequence and EMRS

addressing suitable for mobile equipments. When the en_lowpower_mode parameter is

cleared to 1'b0, a standard DDR SDRAM or SDRAM device may be used.

RM0319 数据表(PDF) 86 Page - STMicroelectronics

RM0319 数据表(HTML) 86 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载